Interfacing Reconfigurable Logic with a CPU

Reconfigurable computing devices have achieved substantial performance improvements over conventional processors on some computational kernels. These benefits derive from hardware customization which avoids the mismatch between the basic requirements of the algorithms and the architectures of the processors. A reconfigurable fabric alone is not sufficient for general-purpose computing since it can be ill-suited to executing entire programs due to space limitations, dataflow-centricity, and inefficiency at implementing some operations (e.g. floating-point arithmetic). These observations have led to the appearance of numerous designs which place some form of reconfigurable logic under the control of a general-purpose processor. In this abstract we explore the ways in which a reconfigurable fabric can be interfaced with a general-purpose processor. While off-chip reconfigurable fabrics have proven to be quite effective at performing streaming, data-intensive computations, they require large streams of data to overcome the latency between the devices. Here we explore the design space for an on-chip fabric, i.e., a reconjigurable function unit(RFU). An RFU allows smaller portions of application to be mapped to the fabric in the form of custom instructions. Though the speedups achieved for streambased computations will in general be much larger than those for custom instructions, they are limited to a smaller class of applications. Custom instructions, however, can be found in a larger class of programs, and compiler techniques can automatically create them. The basic tradeoff in augmenting a processor with a reconfigurable function unit is to maximize both the opportunity for customization and the speedups possible while minimizing hardware costs and runtime overheads. To broaden the range of computations that may be mapped to the fabric, many features are worth considering such as maintaining state in the fabric, supporting simultaneous direct access to many registers, and making memory accessible to the RFU. However, each of these options carries an associated cost in terms of implementation and overhead: saving fabric state on context switches, increasing the number of ports on the register file, and dealing with memory consistency between the processor and the fabric. Several designs have proposed the integration of a given reconfigurable fabric with a general-purpose fixed processor and have reported some exciting performance results. Some important questions have not been answered by these projects, such as: Are there enough opportunities for custom instructions to warrant including them in a hybrid processor design? Which fabric features are essential to attaining speedups for different benchmarks? How many inputs and outputs are needed to support useful custom instructions?